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Cadence Takes Formal Verification to Next Level with Conformal 5.0
Encounter Verification Technology Enhanced with FPGA Support,
Clock Domain Checking, Advanced Datapath Verification
SAN JOSE, Calif.—(BUSINESS WIRE)—Nov. 15, 2004—
Cadence Design Systems, Inc. (NYSE:CDN)(Nasdaq:CDN) today
announced substantial enhancements to its market-leading Encounter(TM)
Conformal(R) technology. Encounter Conformal 5.0 helps customers with
enhanced verification capability to insure that the tapeout accurately
reflects design intent. Important new capabilities in Conformal 5.0
include FPGA support, clock domain checking and advanced datapath
verification.
Conformal technology now extends equivalency checking to FPGA
prototypes through the Synplicity design flow to Xilinx devices, with
support of Altera devices to follow. The product also addresses the
rapid increase in the number and complexity of clock domains with
formal verification of clock domain crossings. This release of
Conformal features SystemVerilog support, complex datapath
verification enhancements, and across-the-board equivalence checking
capacity and performance improvements.
"Conformal is the only solution that can prove that our FPGA
prototype netlist is functionally identical to our high-end ASIC
production design," said Ulrich Hummel, manager, CAD/CAE at Micronas.
"Its ability to verify FPGA synthesis and place and route, along with
its extensive debug and ease-of-use features, makes Conformal a
required formal verification technology in our FPGA design flow."
"The additional capability of Conformal technology to formally
verify our complex clock domain crossing functionality has been
beneficial to us," said Hiroshi Furukawa, Assistant Manager, 3rd
System-on-a-Chip Design Group, System-on-a-Chip Design Division, NEC
Micro Systems, LTD. "Simulation is not well suited for this type of
verification, and now we are able to exhaustively verify that our
clock domains have been correctly implemented."
Conformal technology checks the functional equivalence of versions
of a design at various critical stages to help the designer quickly
identify and correct errors. Conformal equivalence checker does not
share technology with design tools, ensuring an independent
verification audit of the design flow. This complete, independent
verification minimizes design re-spin risk. With thousands of
tapeouts, Conformal technology is the industry's most widely supported
equivalence checking solution.
"Conformal 5.0 substantiates the Cadence investment in the
Conformal formal verification technology acquired with Verplex last
year," said Michael Chang, vice president of R&D in the Cadence Formal
Verification division. "We are constantly enhancing this technology to
compress the verification cycle and meet the challenges of
next-generation designs."
Conformal 5.0, now part of the Cadence Encounter digital IC design
platform, is shipping now.
About Cadence
Cadence is the world's largest supplier of electronic design
technologies and engineering services. Cadence products and services
are used to accelerate and manage the design of semiconductors,
computer systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics based products. With
approximately 4,850 employees and 2003 revenues of approximately $1.1
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN. More information is available at
www.cadence.com.
Cadence, the Cadence logo, and Conformal are registered trademarks
of Cadence Design Systems in the United States and other countries.
Encounter is a trademark of Cadence Design Systems. All other
trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302
jerkanat@cadence.com
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